The Model 4 shipped with TRSDOS 6, an enhanced version of LDOS by Logical Systems and a vastly superior operating system to Tandys earlier TRSDOS offerings. When the Model 4 booted into TRSDOS 6 the video display switched into 80×24 mode and the entire 64KB address space was mapped as RAM. The Model 4 was also capable of running all Model 3 software when a Model 3 operating system disk was detected and loaded during bootup with a 64×16 video mode and Model 3 ROMs mapped from address zero.
The Model 4 also had the ability to display 640×240 or 512×192 high-resolution monochrome graphics with an optional board. A "luggable" version known as the Model 4P (1983) was a self-contained unit with a case design similar to that of a portable sewing machine.
JL, te dice algo esto, al intentar hacer boot con el disco de TRDOS .... no tendrá nada que ver lo que le pasa al hacer boot ?
Pues si, al hacer un POKE 16912,104 la pantalla se pone como cuando carga el TRDOS, de hecho ves que en la pantalla sucede algo pero se pinta como se ve en la foto, espero que sea por la falta de memoria, o igual es que algo hay que revisar.
El modo de 80 columnas es el que me causa eso, lo tengo más que claro y cuando le metes el POKE 16912,104 , seguramente sea algo relacionado, ahora a investigar.
He comprobado con un HIMEM la RAM y me devuelve un FFFF ( 65535 ) , pinta OK.
3.1.8 Video Circuit
The heart of the video display circuit in the Model 4P is the 68045 Cathode Ray Tube Controller (CRTC), U85 The CRTC
is a preprogrammed video controller that provides two screen formats 64 by 16 and 80 by 24 The format is controlled by pin
3 of the CRTC (8064*) The CRTC generates all of the necessary signals required for the video display These signals are
VSYNC (Vertical Sync), HSYNC (Horizontal Sync) for proper sync of the monitor, DISPEN (Display Enable) which indicates
when video data should be output to the monitor, the refresh memory addresses (MAO-MA 13) which addresses the video
RAM, and the row addresses (RAO-RA4) which indicates which scan line row is being displayed The CRTC also provides hardware
scrolling by writing to the internal Memory Start Address Register by OUTmg to Port 88H The internal cursor control of
the 68045 is not used in the Model 4P video circuit.
Since the 80 by 24 screen requires 1,920 screen memory locations, a 2K by 8 static RAM (U82) is used for the video RAM
Addressing to the video RAM (U82) is provided by the 68045 when refreshing the screen and by the CPU when updating of
the data is performed These two sets of address lines are multiplexed by three 74LS157s (U83, U84, and U104) The multiplexers
are switched by CRTCLK which allows the CRTC to address the video RAM during the high state of CRTCLK and
the CPU access during the low state A10 from the CPU is controlled by PAGE* which allows two display pages in the 64 by
16 format When updates to the video RAM are performed by the CPU, the CPU is held in a WAIT state until the CRTC is not
addressing the video RAM This operation allows reads and writes to video RAM without causing hashing on the screen
The circuit that performs this function is a 74LS244 buffer (U103), an 8 bit transparent latch, 74LS373 (U102) and a Delay
line circuit shared with Dynamic RAM timing circuit consisting Of a 74LS74 (U95), 74LS32 (U94), 74LS04 (U74), 74LSOO
(U96), 74LS02 (U75), and Delay Line (U97) During a CPU Read Access to the Video RAM, the address is decoded by the
PAL U109 and asserts VIDEO* low This is inverted by U74 (1/6 of 74LS04) which pulls one input of U96 (1/4 of 74LSOO) and
in turn asserts VWAIT * low to the CPU RD is high at this time and is latched into U95 (1/2 of 74LS74) on the rising edge of
XADR7* XADR7* is inverse of CRTCLK which drives the CRTC