RetroWiki & Cacharreo [RW]

FPGA cores are not interchangeable. Each core is compiled for an specific FPGA chip and how FPGA pins are wired to other components in that board.

Kyp escribió:But it is possible to modify the design to run with just 32K o BRAM

Didn't you read this part?
It is possible to put ROM data into BRAM and, at start, dump it into SRAM thus leaving BRAM to work as VRAM.

IMHO with a standard Lynx 96K it is only possible to have 80 cols in green. 80 columns x 24 rows x 8 lines per row = 15360 bytes. To get full color we need three 16K pages but we only have two. Leaving the blue/red page blank to avoid fancy effects we only have the green/altgreen page to display data.

48K of BRAM is required to run Lynx 48K (16K for ROM and 32K for VRAM). That FPGA only has 40K from BRAM, so as is it won't work.
But it is possible to modify the design to run with just 32K o BRAM

jltursan escribió:The Lynx banking scheme is a real nightmare
I don't remember how the 96KB has its memory banked

It has the same four banks ROM/User RAM/Video RAM/Extra ROM than the 48K but user RAM is 64K instead of 8K, and ROM is 24K (3x8K) instead of 16K (2x8K)

To have 80 columns it is necessary to read data twice as fast. In any case, that does not affect the FPGA implementation where the RAM chips are much faster than necessary. I just need to change some clock speeds and the patched ROM. In the original hardware, changing the ROM we get 80 columns in BA...

I think I was confusing the splynx mod with the 80 column mod. Any information about that 80 column mod? BTW, I don't think there are problems with interruptions in the FPGA implementation, there are no multiplexer chips, memory subsystem is completely different.

Is there some kind of explanation about that SPLYNX modifications? Something more like a 'theory of operation' than some schematics mods. It would be great if I can add this modifications to my FPGA core.

Si pero para mantener la hora se usan baterías... Y odio los chip Dallas o las baterías soldadas... Donde esté un portapilas.... Pondré una pila de litio tipo CR2032, las baterías son un peligro. Si es para uso serio tiene cierto sentido lo que apuntas...para jugar o cosas que ni fu ni fa pues en m...

En PCBWay hay IDE para a500 pero tiene problema de no hacer boot, en tu supuesto futuro IDE haria boot desde minimo 1.3? Mi intención es que sea compatible con el IDE del A600/A1200. No se si desde 1.3 se podrá arrancar (diría que no) o hará falta un KS 2.05 o superior. ¿Con tan pocos componentes? ...

Remember this is a quick drawing based on how the joystick works in my FPGA implementation. I can't be sure it works.
I don't have a real Lynx to test it.

Mola!!! Sobre todo para los 500, que poner fast siempre ha sido un poco difícil. Sobre todo es que sea barato. Uso chips DRAM que son mucho más baratos que los SRAM que se suelen usar en las aceleradoras. Tienes ECS en tu Amiga? Vale para OCS? Es un A500 R6 y vino así, aunque no se si el anterior p...

That scheme is completely wrong.
I have made a quick drawing of this (needs revision):

Este es un proyecto que empecé hace ya más de un año pero que por unas cosas o por otras me ha costado mucho avanzar :roll: De momento, para ir creando un poco de expectación, unas fotos -grin https://i.postimg.cc/3w8PRFBs/Ami-RAM-01.jpg https://i.postimg.cc/Z5FG4MrP/Ami-RAM-02.jpg https://i.postimg...

invacuo escribió:En principio la idea es buscar algún 16K o 48K que funcione y usar esa CPU de donante. Para así estar seguro que la CPU le va.

Pobre Spectrum

Muy interesante. A ver que tal esos microdrives